View NCV890231MWTXG_8352934.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2015 february, 2015 ? rev. 2 1 publication order number: ncv890231/d ncv890231 2.0 a, 2 mhz automotive buck switching regulator the ncv890231 is a fixed?frequency, monolithic, buck switching regulator intended for automotive, battery?connected applications that must operate with up to a 36 v input supply. the regulator is suitable for systems with low noise and small form factor requirements often encountered in automotive driver information systems. the ncv890231 is capable of converting the typical 4.5 v to 18 v automotive input voltage range to outputs as low as 3.3 v at a constant switching frequency above the sensitive am band, eliminating the need for costly filters and emi countermeasures. two pins are provided to synchronize switching to a clock, or to another ncv890231. the ncv890231 also provides several protection features expected in automotive power supply systems such as current limit, short circuit protection, and thermal shutdown. in addition, the high switching frequency produces low output voltage ripple even when using small inductor values and an all?ceramic output filter capacitor ? forming a space?ef ficient switching regulator solution. features ? internal n?channel power switch ? low v in operation down to 4.5 v ? high v in operation to 36 v ? withstands load dump to 45 v ? 2 mhz free?running switching frequency ? auto?synchronizes with other ncv890231 or to an external clock ? logic level enable input can be directly tied to battery ? 2.2 a (min) cycle?by?cycle peak current limit ? short circuit protection enhanced by frequency foldback ? 1.75% output voltage tolerance ? output voltage adjustable down to 0.8 v ? 1.4 millisecond internal soft?start ? thermal shutdown (tsd) ? low shutdown current ? wettable flanks ? dfn ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant applications ? audio ? infotainment ? safety ? v ision systems ? instrumentation vin drv synco gnd en sw bst synci fb comp vin sync out en vout cin cbst dbst dfw rcomp ccomp cout l1 cdrv ncv890231 rfb2 rfb1 sync in 1 2 3 4 56 7 8 9 10 figure 1. typical application dfn10 case 485c marking diagram a = assembly location l = wafer lot y = year w = work week = pb?free device (note: microdot may be in either location) v8902 31 alyw see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information www. onsemi.com
ncv890231 www. onsemi.com 2 figure 2. ncv890231 block diagram vin drv gnd en sw bst fb comp vin enable vout cin cbst dbst dfw rcomp ccomp cout l1 cdrv pwm logic off on + ? oscillator + ? soft?start reset 3.3 v reg voltages monitors tsd + + + 2 a synco sync out out sync in synci sync in
ncv890231 www. onsemi.com 3 maximum ratings rating symbol value unit min/max voltage vin ?0.3 to 45 v max voltage vin to sw 45 v min/max voltage sw ?0.7 to 40 v min voltage sw ? 20ns ?3.0 v min/max voltage bst ?0.3 to 40 min/max voltage bst to sw ?0.3 to 3.6 v min/max voltage on en ?0.3 to 40 v min/max voltage comp ?0.3 to 2 v min/max voltage fb ?0.3 to 18 v min/max voltage synco ?0.3 to 3.6 v min/max voltage drv ?0.3 to 3.6 v min/max voltage synci ?0.3 to 6 v thermal resistance, 3x3 dfn junction?to?ambient* r ja 50 c/w storage temperature range ?55 to +150 c operating junction temperature range t j ?40 to +150 c esd withstand voltage human body model machine model charge device model v esd 2.0 200 >1.0 kv v kv moisture sensitivity msl level 1 peak reflow soldering temperature 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *mounted on 1 sq. in. of a 4?layer pcb with 1 oz. copper thickness.
ncv890231 www. onsemi.com 4 figure 3. pin connections 1 vin 10 sw 2 drv 3 synco 4 gnd 9 bst 8 synci 7 fb (top view) 5 en 6 comp pin function descriptions pin no. symbol description 1 vin input voltage from battery. place an input filter capacitor in close proximity to this pin. 2 drv output voltage to provide a regulated voltage to the power switch gate driver. 3 synco synchronization output. turn?on of the power switch causes the synco signal to fall. synco rises half a switching period later. connecting to the synci pin of another ncv890231 causes them to switch out?of?phase 4 gnd battery return, and output voltage ground reference. 5 en this ttl compatible enable input allows the direct connection of battery as the enable signal. grounding this input stops switching and reduces quiescent current draw to a minimum. 6 comp error amplifier output, for tailoring transient response with external compensation components. 7 fb feedback input pin to program output voltage, and detect pre?charged or shorted output conditions. 8 synci synchronization input. connecting an external clock to the synci pin synchronizes switching to the ris- ing edge of the synci voltage. 9 bst bootstrap input provides drive voltage higher than vin to the n?channel power switch for optimum switch r ds(on) and highest efficiency. 10 sw switching node of the regulator. connect the output inductor and cathode of the freewheeling diode to this pin. exposed pad connect to pin 4 (electrical ground) and to a low thermal resistance path to the ambient temperature environment.
ncv890231 www. onsemi.com 5 electrical characteristics (v in = 4.5 v to 28 v, v en = 5 v, v bst = v sw + 3.0 v, c drv = 0.1 f, min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter symbol conditions min typ max unit quiescent current quiescent current, shutdown i qsd v in = 13.2 v, v en = 0 v, t j = 25 c 10 a quiescent current, enabled i qen v in = 13.2 v 3.0 ma undervoltage lockout ? vin (uvlo) uvlo start threshold v uvlstt v in rising 4.1 4.5 v uvlo stop threshold v uvlstp v in falling 3.9 4.4 v uvlo hysteresis v uvlohy 0.1 0.2 v enable (en) logic low v enlo 0.8 v logic high v enhi 2.0 v input current i en 8.0 30 a soft?start (ss) soft?start completion time t ss 0.8 1.4 2.0 ms voltage reference fb pin voltage during regulation v fbr comp shorted to fb 0.786 0.8 0.814 v error amplifier fb bias current i fbbias v fb = 0.8 v 0.25 1.0 a transconductance g m g m(hv) v comp = 1.3 v 4.5 v < v in < 18 v 20 v < v in < 28 v 0.6 0.3 1.0 0.5 1.5 0.75 mmho output resistance r out 1.4 m comp source current limit i source v fb = 0.63 v, v comp = 1.3 v 4.5 v < v in < 18 v 20 v < v in < 28 v 75 40 a comp sink current limit i sink v fb = 0.97 v, v comp = 1.3 v 4.5 v < v in < 18 v 20 v < v in < 28 v 75 40 a minimum comp voltage v cmpmin v fb = 0.97 v 0.2 0.7 v oscillator frequency f sw f sw(hv) 4.5 < v in < 18 v 20 v < v in < 28 v 1.8 0.9 2.0 1.0 2.2 1.1 mhz vin frequency foldback monitor frequency foldback threshold v in rising v in falling v fldup v flddn v fb = 0.63 v 18.4 18 20 19.8 v frequency foldback hysteresis v fldhy 0.2 0.3 0.4 v synchronization synco output pulse duty ratio d (sync) c load = 40 pf 40 60 % synco output pulse falltime t r(sync) c load = 40 pf, 90% to 10% 4 ns synco output pulse risetime t f(sync) c load = 40 pf, 10% to 90% 4 ns synci input resistance to ground r h(sync) v synci = 5.0 v 50 200 k synci input high threshold voltage v hsync 2.0 v synci input low threshold voltage v lsync 0.8 v synci high pulse width t hsynci v sync > max v hsync 40 ns 1. not tested in production. limits are guaranteed by design.
ncv890231 www. onsemi.com 6 electrical characteristics (v in = 4.5 v to 28 v, v en = 5 v, v bst = v sw + 3.0 v, c drv = 0.1 f, min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol synchronization synci low pulse width t lsynci v sync < min v lsync 40 ns external sync frequency f synci 1.8 2.5 mhz master reassertion time t i(sync) time from last rising synci edge to first un?synchronized turn?on. 650 ns vin overvoltage shutdown monitor overvoltage stop threshold v ovstp 32.4 36 v overvoltage start threshold v ovstt 30 35.4 v overvoltage hysteresis v ovhy 0.6 1.5 2.4 v slope compensation ramp slope (note 1) (with respect to switch current) s ramp s ramp(hv) 4.5 < v in < 18 v 20 v < v in < 28 v 0.7 0.25 1.3 0.6 a/ s power switch on resistance r dson v bst = v sw + 3.0 v 650 m leakage current vin to sw i lksw v en = 0 v, v sw = 0, v in = 18 v 10 a minimum on time t onmin measured at sw pin 45 70 ns minimum off time t offmin measured at sw pin at f sw = 2 mhz (normal) at f sw = 500 khz (max duty cycle) 30 30 50 70 ns peak current limit current limit threshold i lim 2.2 2.45 2.7 a short circuit frequency foldback lowest foldback frequency lowest foldback frequency ? high v in hiccup mode f swaf f swafhv f swhic v fb = 0 v, 4.5 v < v in < 18 v v fb = 0 v, 20 v < v in < 28 v v fb = 0 v 400 200 24 500 250 32 600 300 40 khz gate voltage supply (drv pin) output voltage v drv 3.1 3.3 3.5 v drv por start threshold v drvstt 2.7 2.9 3.05 v drv por stop threshold v drvstp 2.5 2.8 3.0 v drv current limit i drvlim v drv = 0 v 16 45 ma output precharge detector threshold voltage v ssen 20 35 50 mv thermal shutdown activation temperature (note 1) t sd 150 190 c hysteresis (note 1) t hys 5 20 c 1. not tested in production. limits are guaranteed by design. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncv890231 www. onsemi.com 7 typical characteristics curves 0 1 2 3 4 5 6 7 8 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) i qsd . shutdown quiescent current ( a) figure 4. shutdown quiescent current vs. junction temperature v in = 13.2 v 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) i qen . enabled quiescent current (ma) figure 5. enabled quiescent current vs. junction temperature 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) v uvlstt . uvlo start threshold (v) figure 6. uvlo start threshold vs. junction temperature 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) v uvlstp . uvlo stop threshold (v) figure 7. uvlo stop threshold vs. junction temperature 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) t ss . soft?start duration (ms) figure 8. soft?start duration vs. junction temperature 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 ?50 ?25 0 25 50 75 100 125 150 v fbr . fb regulation voltage (v) t j . junction temperature ( c) figure 9. fb regulation voltage vs. junction temperature
ncv890231 www. onsemi.com 8 typical characteristics curves 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) g m . error amplifier transconductance (ms) figure 10. error amplifier transconductance vs. junction temperature v in = 4.5 v v in = 28 v 20 30 40 50 60 70 80 90 100 ?50 ?25 0 25 50 75 100 125 15 0 t j . junction temperature ( c) i source . error amplifier sourcing current ( a) figure 11. error amplifier max sourcing current vs. junction temperature v in = 4.5 v v in = 28 v 20 30 40 50 60 70 80 90 100 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) i sink . error amplifier sinking current ( a) figure 12. error amplifier max sinking current vs. junction temperature v in = 4.5 v v in = 28 v 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 ?50 ?25 0 25 50 75 100 125 15 0 t j . junction temperature ( c) f sw . oscillator freqency (mhz) figure 13. oscillator frequency vs. junction temperature v in = 13.2 v v in = 28 v 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 ?50 ?25 0 25 50 75 100 125 150 t j . junction temperature ( c) v fldup . v flddn , freq. foldback threshold (v) figure 14. rising frequency foldback threshold vs. junction temperature 48 49 50 51 52 53 54 55 56 ?50 ?25 0 25 50 75 100 125 15 0 d (sync) . synco pulse duty ratio (%) t j . junction temperature ( c) figure 15. synco pulse duty ratio vs. junction temperature v fldup v flddn
ncv890231 www. onsemi.com 9 typical characteristics curves 40 60 80 100 120 140 160 ?50 ?25 0 25 50 75 100 125 150 r h(sync) . synci input resistance (k ) t j . junction temperature ( c) figure 16. synci input resistance vs. junction temperature 0 100 200 300 400 500 600 700 800 900 ?50 ?25 0 25 50 75 100 125 0 15 r ds(on) . power switch on resistance (m ) t j . junction temperature ( c) figure 17. power switch r ds(on) vs. junction temperature 40 45 50 55 60 65 70 75 80 ?50 ?25 0 25 50 75 100 125 150 t onmin . minimum time (ns) t j . junction temperature ( c) figure 18. minimum on time vs. junction temperature 35 40 45 50 55 60 65 70 75 ?50 ?25 0 25 50 75 100 125 150 t offmin . minimum time (ns) t j . junction temperature ( c) figure 19. minimum off time vs. junction temperature 2.00 2.10 2.20 2.30 2.40 2.50 2.60 ?50 ?25 0 25 50 75 100 125 150 i lim , peak current limit (a) t j . junction temperature ( c) figure 20. current limit threshold vs. junction temperature 200 250 300 350 400 450 500 550 600 ?50 ?25 0 25 50 75 100 125 150 f swaf . foldback mode switching frequency (khz) t j . junction temperature ( c) figure 21. short?circuit foldback frequency vs. junction temperature v in = 4.5 v v in = 28 v 2.70 2.80 2.90
ncv890231 www. onsemi.com 10 typical characteristics curves 24 26 28 30 32 34 36 38 40 ?50 ?25 0 25 50 75 100 125 150 f swhc . hiccup mode freuqncy (khz) t j . junction temperature ( c) figure 22. hiccup mode switching frequency vs. junction temperature 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 ?50 ?25 0 25 50 75 100 125 150 v drv . drv voltage (v) t j . junction temperature ( c) figure 23. drv voltage vs. junction temperature i drv = 0 ma i drv = 16 ma 2.5 2.6 2.7 2.8 2.9 3.0 3.1 ?50 ?25 0 25 50 75 100 125 150 v drvstt . v drvstp , drv reset thresholds (v) t j . junction temperature ( c) figure 24. drv reset threshold vs. junction temperature v drvstt v drvstp 21 22 23 24 25 26 27 28 29 30 ?50 ?25 0 25 50 75 100 125 150 i drvlim . drv current limit (ma) 20 25 30 35 40 45 50 55 ?50 ?25 0 25 50 75 100 125 150 v ssen . output precharge detector threshold (v) t j . junction temperature ( c) figure 25. drv current limit vs. junction temperature figure 26. output precharge detector threshold vs. junction temperature t j . junction temperature ( c)
ncv890231 www. onsemi.com 11 general information input voltage an undervoltage lockout (uvlo) circuit monitors the input, and inhibits switching and resets the soft?start circuit if there is insufficient voltage for proper regulation. the ncv890231 can regulate a 3.3 v output with input voltages above 4.5 v and a 5.0 v output with an input above 6.5 v. the ncv890231 automatically terminates switching if input voltage exceeds v ovstp (see figure 27), and withstands input voltages up to 45 v. to limit the power lost in generating the drive voltage for the power switch, the switching frequency is reduced by a factor of 2 when the input voltage exceeds the v in frequency foldback threshold v fldup (see figure 27). frequency reduction is automatically terminated when the input voltage drops back below the v in frequency foldback threshold v flddn . figure 27. ncv890231 switching frequency reduction at high input voltage 4 18 20 36 vin (v) 1 2 45 30 fsw (mhz) enable the ncv890231 is designed to accept either a logic level signal or battery voltage as an enable signal. en low induces a ?sleep mode? which shuts off the regulator and minimizes its supply current to a couple of a typically (i qsd ) by disabling all functions. upon enabling, voltage is established at the drv pin, followed by a soft?start of the switching regulator output. soft?start upon being enabled or released from a fault condition, and after the drv voltage is established, a soft?start circuit ramps the switching regulator error amplifier reference voltage to the final value. during soft?start, the average switching frequency is lower than its normal mode value (typically 2 mhz) until the output voltage approaches regulation. slope compensation a fixed slope compensation signal is generated internally and added to the sensed current to avoid increased output voltage ripple due to bifurcation of inductor ripple current at duty cycles above 50%. the fixed amplitude of the slope compensation signal requires the inductor to be greater than a minimum value, depending on output voltage, in order to avoid sub?harmonic oscillations. for 3.3 v and 5 v output voltages, the recommended inductor value is 4.7 h. short circuit frequency foldback during severe output overloads or short circuits, the ncv890231 automatically reduces its switching frequency. this creates duty cycles small enough to limit the peak current in the power components, while maintaining the ability to automatically reestablish the output voltage if the overload is removed. if the current is still too high after the switching frequency folds back to 500 khz, the regulator enters an auto?recovery burst mode that further reduces the dissipated power. current limiting due to the ripple on the inductor current, the average output current of a buck converter is lower than the peak current setpoint of the regulator. figure 28 shows ? for a 4.7 h inductor ? how the variation of inductor peak current with input voltage affects the maximum dc current the ncv890231 can deliver to a load. figure 28. ncv890231 load current capability with 4.7 h inductor 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 0 5 10 15 20 25 30 35 40 input voltage (v) minimum current limit (a) (5 v out ) (3.3 v out )
ncv890231 www. onsemi.com 12 synchronization two ncv890231 can be synchronized out?of?phase to one another by connecting the synco pin of one to the synci pin of the other (figure 29). any number of ncv890231 can also be synchronized to an external clock (figure 30). if a part does not have its switching frequency controlled by the synci input, it drives the synco pin low when it turns on the power switch, and drives it high half a switching period later. when the switching frequency is controlled by the synci input, the synco pin is held low. synchronization starts within 2 ms of soft?start completion. a rising edge at the synci pin causes an ncv890231 to immediately turn on the power switch. if another rising edge does not arrive at the synci pin within the master reassertion time, the ncv890231 controls its own switching frequency, allowing uninterrupted operation in the event that the clock (or controlling ncv890231) is turned off. if internal conditions or excessive input voltage cause an ncv890231 to fold back its switching frequency, the main oscillator switching frequency is no longer derived from the frequency received at the synci pin. under these conditions, the synco pin is held low. an external pulldown resistor is not required at the synci pin if it is unconnected. vin drv synco gnd en sw bst synci fb comp vout1 cin1 cbst 1 dbst1 dfw1 rcomp1 ccomp1 cout1 l1 cdrv1 rfb2 rfb1 1 2 3 4 56 7 8 9 10 vin drv synco gnd en sw bst synci fb comp vin synchronization en2 vout2 cin2 cbst2 dbst2 dfw2 rcomp2 ccomp2 cout2 l2 cdrv2 ncv890231 rfb2 rfb1 1 2 3 4 56 7 8 9 10 sync master sync slave figure 29. ncv890231s synchronized to each other master enabled by battery ncv890231 vin drv synco gnd en sw bst synci fb comp vout1 cin1 cbst 1 dbst1 dfw1 rcomp1 ccomp1 cout1 l1 cdrv1 rfb12 rfb11 1 2 3 4 56 7 8 9 10 vin drv synco gnd en sw bst synci fb comp vin synchronization en2 vout2 cin2 cbst2 dbst2 dfw2 rcomp2 ccomp2 cout2 l2 cdrv 2 ncv890231 rfb22 rfb21 1 2 3 4 56 7 8 9 10 clk figure 30. both ncv890231s synchronized to external clock #1 enabled by battery ncv890231
ncv890231 www. onsemi.com 13 bootstrap at the drv pin an internal regulator provides a ground?referenced voltage to an external capacitor (c drv ), to allow fast recharge of the external bootstrap capacitor (c bst ) used to supply power to the power switch gate driver. if the voltage at the drv pin goes below the drv uvlo threshold v drvstp , switching is inhibited and the soft?start circuit is reset, until the drv pin voltage goes back up above v drvstt . in order for the bootstrap capacitor to stay charged, the switch node needs to be pulled down to ground regularly. in very light load condition, the ncv890231 skips switching cycles to ensure the output voltage stays regulated. when the skip cycle repetition frequency gets too low, the bootstrap voltage collapses and the regulator stops switching. practically, this means that the ncv890231 needs a minimum load to operate correctly. figure 31 shows the minimum current requirements for different input and output voltages. input voltage (v) 9.2 8.2 7.2 6.2 5.2 4.2 0 10 20 30 40 50 minimum output current (ma) minimum load 5 v out input voltage (v) 7.2 6.7 6.2 5.7 5.2 4.7 4.2 0 2 4 8 12 14 minimum output current (ma) minimum load 3.3 v out 6 10 16 input voltage (v) 7.2 6.7 6.2 5.2 4.7 4.2 0 4 8 12 16 20 minimum output current (ma) minimum load 3.7 v out input voltage (v) 10.2 8.2 6.2 4.2 0 5 10 25 35 45 minimum output current (ma) minimum load 5.5 v out 15 30 50 figure 31. minimum load current with different input and output voltages l = 2.2 h l = 4.7 h l = 2.2 h l = 4.7 h 5.7 2 6 10 14 18 l = 2.2 h l = 4.7 h l = 2.2 h l = 4.7 h 20 40
ncv890231 www. onsemi.com 14 output precharge detection prior to soft?start, the fb pin is monitored to ensure the sw voltage is low enough to have charged the external bootstrap capacitor (c bst ). if the fb pin is higher than v ssen , restart is delayed until the output has discharged. figure 32 shows the ic starts to switch after the voltage on fb pin reaches vssen, even the en pin is high. after the ic is switching, the fb pin follows the soft starts reference to reach the final set point. figure 32. output voltage detection en fb sw time time time v ssen thermal shutdown a thermal shutdown circuit inhibits switching, resets the soft?start circuit, and removes drv voltage if internal temperature exceeds a safe level. switching is automatically restored when temperature returns to a safe level. minimum dropout voltage when operating at low input voltages, two parameters play a major role in imposing a minimum voltage drop across the regulator: the minimum off time (that sets the maximum duty cycle), and the on state resistance. when operating in continuous conduction mode (ccm), the output voltage is equal to the input voltage multiplied by the duty ratio. because the ncv890231 needs a sufficient bootstrap voltage to operate, its duty cycle cannot be 100%: it needs a minimum off time (t offmin ) to periodically re?fuel the bootstrap capacitor c bst . this imposes a maximum duty ratio d max = 1 ? t offmin .f sw(min) , with the switching frequency being folded back down to f sw(min) = 500 khz to keep regulating at the lowest input voltage possible. the drop due to the on?state resistance is simply the voltage drop across the switch resistance r dson at the given output current: v swdrop = i out .r dson . which leads to the maximum output voltage in low vin condition: v out = d max .v in(min) ? v swdrop figure 33. minimum input voltage vs. output current i out (a) 1.2 0.8 1.0 0.6 0.2 0 0 1 2 3 4 5 6 7 v in (v) 0.4 1.4 1.6 1.8 2.0 v out = 5 v exposed pad the exposed pad (epad) on the back of the package must be electrically connected to the electrical ground (gnd pin) for proper, noise?free operation. design methodology the ncv890231 being a fixed?frequency regulator with the switching element integrated, is optimized for one value of inductor. this value is set to 4.7 h, and the slope compensation is adjusted for this inductor. the only components left to be designed are the input and output capacitor and the freewheeling diode. please refer to the design spreadsheet www.onsemi.com ncv890231 page that helps with the calculation. output capacitor: the minimum output capacitor value can be calculated based on the specification for output voltage ripple: c out min i l 8 v out f sw (eq. 1) with ? i l the inductor ripple current: i l v out 1 v out v in l f sw (eq. 2) ? v out the desired voltage ripple. however, the esr of the output capacitor also contributes to the output voltage ripple, so to comply with the requirement, the esr cannot exceed r esrmax : r esr max v out l f sw v out 1 v out v in (eq. 3) finally, the output capacitor must be able to sustain the ac current (or rms ripple current): i outac i l 23 (eq. 4)
ncv890231 www. onsemi.com 15 typically, with the recommended 4.7 h inductor, two ceramic capacitors of 10 f each in parallel give very good results. freewheeling diode: the diode must be chosen according to its maximum current and voltage ratings, and to thermal considerations. as far as max ratings are concerned, the maximum reverse voltage the diode sees is the maximum input voltage (with some mar gin in case of ringing on the switch node), and the maximum forward current the peak current limit of the ncv890231, i lim . the power dissipated in the diode is p dloss : p dloss i out 1 v out v in v f i drms r d (eq. 5) with: ?i out the average (dc) output current ?v f the forward voltage of the diode ?i drms the rms current in the diode: i drms ( 1 d ) i out 2 i l 2 12 (eq. 6) ?r d the dynamic resistance of the diode (extracted from the v/i curve of the diode in its datasheet). then, knowing the thermal resistance of the package and the amount of heatsinking on the pcb, the temperature rise corresponding to this power dissipation can be estimated. input capacitor: the input capacitor must sustain the rms input ripple current i inac : i inac i l 2 d 3 (eq. 7) it can be designed in combination with an inductor to build an input filter to filter out the ripple current in the source, in order to reduce emi conducted emissions. for example, using a 4.7 h input capacitor, it is easy to calculate that an inductor of 200 nh will ensure that the input filter has a cut?off frequency below 200 khz (low enough to attenuate the 2 mhz ripple). error amplifier and loop transfer function the error amplifier is a transconductance type amplifier. the output voltage of the error amplifier controls the peak inductor current at which the power switch shuts off. the current mode control method employed allows the use of a simple, type ii compensation to optimize the dynamic response according to system requirements. figure 34 shows the error amplifier with the compensation components and the voltage feedback divider. g m * v vref vout rfb1 rfb 2 r o rcomp ccomp cp v fb v vcomp figure 34. feedback compensator network model the transfer function from vout to vcomp is the product of the feedback voltage divider and the error amplifier. gdivider(s) rfb2 rfb1 rfb2 (eq. 8) gerr amp(s) gm ro 1 s z 1 s pl 1 s ph (eq. 9) z 1 rcomp ccomp (eq. 10) pl 1 ro ccomp (eq. 11) ph 1 rcomp cp (eq. 12) the output resistor ro of the error amplifier is 1.4 m and gm is 1 ma/v . the capacitor cp is for rejecting noise at high frequency and is integrated inside the ic with a value of 18 pf. the power stage transfer function (from vcomp to output) is shown below: gps(s) rload ri 1 1 rload tsw l [ mc (1 d) 0.5 ] 1 s z 1 s p fh(s) (eq. 13) z 1 resr cout (eq. 14) p 1 rload cout mc (1 d) 0.5 l cout fsw (eq. 15)
ncv890231 www. onsemi.com 16 where mc 1 se sn (eq. 16) sn vin vout l ri (eq. 17) ri represents the equivalent sensing resistor which has a value of 0.183 , se is the compensation slope which is 183 kv/s, sn is the slope of the sensing resistor current during on time. fh(s) represents the sampling effect from the current loop which has two poles at one half of the switching frequency: fh(s) 1 1 s n qp s 2 n 2 (eq. 18) n fsw qp 1 [ mc (1 d) 0.5 ] (eq. 19) the total loop transfer function is the product of power stage and feedback compensation network. gloop(s) gdivider(s) gerr amp(s) gps(s) (eq. 20) the bode plots of the open loop transfer function will show the gain and phase margin of the system. the compensation network is designed to make sure the system has enough phase margin and bandwidth. design of the compensation network the function of the compensation network is to provide enough phase margin at crossover frequency to stabilize the system as well as to provide high gain at low frequency to eliminate the steady state error of the output voltage. please refer to the design spreadsheet www.onsemi.com ncv890231 page that helps with the calculation. the design steps will be introduced through an example. example: vin = 15.5 v, vout = 3.3 v, rload = 1.65 , iout = 2 a, l = 4.7 h, cout = 20 f (resr = 7 m ) the reference voltage of the feedback signal is 0.8 v and to meet the minimum load requirements, select rfb1 = 100 , rfb2 = 31.6 . from the specification, the power stage transfer function can be plotted as below: figure 35. power stage bode plots 100 110 3 ? 110 4 ? 110 5 ? 110 6 ? 90 ? 45 ? 0 45 90 180 ? 90 ? 0 90 180 (hz) (db) 20 x log gps f m () ?? ?? arg gps f m () () 180 f m x the crossover frequency is chosen to be fc = 70 khz, the power stage gain at this frequency is ?4 db (0.634) from calculation. then the gain of the feedback compensation network must be 4 db. next is to decide the locations of one zero and one pole of the compensator. the zero is to provide phase boost at the crossover frequency and the pole is to reject the noise of high frequency. in this example, a zero is placed at 1/10 of the crossover frequency and a pole is placed at 1/5 of the switching frequency (fsw = 2 mhz): fz = 7000 hz, fp = 400000 hz, rcomp, ccomp and cp can be calculated from the following equations: rcomp fp gm (fp fz) | gps(fc) | vout vref 1 fc fp 2 1 fz fc 2 (eq. 21) ccomp 1 2 fz rcomp (eq. 22) cp 1 2 fp rcomp (eq. 23) note: there is an 18 pf capacitor at the output of the ota integrated in the ic, and if a larger capacitor needs to be used, subtract this value from the calculated cp. figure 36 shows cp is split into two capacitors. cint is the 18 pf in the ic. cext is the extra capacitor added outside the ic.
ncv890231 www. onsemi.com 17 from the calculation: rcomp = 6.6 k , ccomp = 3.4 nf, cp = 48 pf so the feedback compensation network is as below: figure 36. example of the feedback compensation network vref vout rfb1 rfb2 ro rcomp ccomp cint v fb v vcomp 31.6 0.8 v 18 pf 6.6 k 3.4 nf cext 30 pf 100 g m *v figure 37 shows the bode plot of the ota compensator 100 110 3 ? 110 4 ? 110 5 ? 110 6 ? 90 ? 45 ? 0 45 90 180 ? 90 ? 0 90 180 (hz) (db) 20 x log gerr_amp f m () ?? ?? arg gerr_amp f m () () 180 f m figure 37. bode plot of the ota compensator x the total loop bode plot is as below: figure 38. bode plot of the total loop 100 110 3 ? 110 4 ? 110 5 ? 110 6 ? 90 ? 45 ? 0 45 90 180 ? 90 ? 0 90 180 (hz) (db) 20 x log gloop f m () ?? ?? arg gloop f m () () 180 f m the crossover frequency is at 70 khz and phase margin is 75 degrees.
ncv890231 www. onsemi.com 18 pcb layout recommendation as with any switching power supplies, there are some guidelines to follow to optimize the layout of the printed circuit board for the ncv890231. however, because of the high switching frequency extra care has to be taken. ? minimize the area of the power current loops: ? input capacitor ncv890231 switch inductor output capacitor return through ground ? freewheeling diode inductor output capacitor return through ground ? minimize the length of high impedance signals, and route them far away from the power loops: ? feedback trace ? comp trace ordering information device package shipping ? NCV890231MWTXG dfn10 with wettable flanks (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv890231 www. onsemi.com 19 package dimensions dfn10, 3x3, 0.5p case 485c issue b 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv890231/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

▲Up To Search▲

Price & Availability of NCV890231MWTXG

	To Download NCV890231MWTXG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .